This invention relates to a microcomputer and, in particular, to a microcomputer of a variable operation speed type for use in a mobile apparatus such as a mobile telephone and a digital video camera.
In recent years, a microcomputer variable in operation speed is used in various kinds of mobile apparatuses such as a mobile telephone and a digital video camera. With an improvement in function of a mobile apparatus of the type, the microcomputer is also required to be improved in function. Presently, an operation frequency is also increased to the order of 10 times that of the prior art. If a high-speed operation is continuously carried out, power consumption is so large that the life of a battery is shortened. This brings about a decrease in commercial value of the mobile apparatus. As well known in the art, power consumption of a logical circuit portion comprising CMOSs (Complementary Metal Oxide Semiconductors) is increased in proportion to the operation frequency. This means that the power consumption can be suppressed by a low-speed operation. Taking this into account, a low-speed operation mode on the order of 32 KHz is introduced in order to decrease the power consumption. Thus, the power consumption is decreased in a standby period.
For example, in the mobile telephone, the high-speed operation such as speech conversion and communication processing is carried out upon speech communication while the low-speed operation such as a clock function and a key input function alone is performed during the standby period. Typically, the stand-by period is substantially longer than a high-speed operation period. Therefore, a continuous usable time duration of the mobile apparatus can be prolonged to thereby increase the commercial value.
On the other hand, the microcomputer uses as a memory readout circuit an analog circuit such as a sense amplifier in which a high-speed operation is realized by flowing the continuous current. With such analog circuit included, the continuous current flows even during the low-speed operation. Therefore, the power consumption can not be decreased during the low-speed operation. Thus, a problem arises in view of the decrease in power consumption.
As an approach to solve the above-mentioned problem, Japanese Unexamined Patent Publication (JP-A) No. 7296/1990 (Reference 1) discloses a memory circuit included in a conventional microcomputer and intended to reduce power consumption of a read only memory (ROM). During the high-speed operation, a high-speed readout operation is carried out by the use of a current-sensing amplifier which is inherently operable at a high speed although a continuous current path is required. During the low-speed operation, low power consumption is achieved by the use of a dynamic readout circuit which has no continuous current path although the operation speed is low.
FIG. 1 shows, in blocks, the memory circuit included in the conventional microcomputer disclosed in Reference 1. The illustrated memory circuit includes ROM cells M3 and M5, each consisting of an N-channel MOS transistor, and a current-sensing amplifier 101. The current-sensing amplifier 101 includes N-channel MOS transistors N12 and N9, P-channel MOS transistors P7 and P8, and an inverter I11 for inverting an electric potential of a node X10 as a common connection point of drains of the transistors N9 and P8 to produce a data signal DI.
The memory circuit further includes N-channel MOS transistors N13, N15, and N16, each forming a switching circuit, P-channel MOS transistors P14, P17, P21, P22, and P28, AND circuits A29 and A30. The AND circuits A29 and A30 have first inputs connected to address lines Al and A2, respectively, second inputs connected to an output of an OR circuit O27 in common, and outputs connected to gates of the transistors M3 and M5, respectively.
An NOR circuit O23 has a first input connected to a data line D4, a second input supplied with an inverted control signal BCS, and an output connected to a gate of the transistor N12. An NOR circuit O24 has a first input connected to a drain of the transistor N16, a second input supplied with the inverted control signal BCS, and an output connected to a gate of the transistor N16.
An inverter I25 inverts a control signal CS to produce the inverted control signal BCS. An OR circuit O27 calculates a logical sum of a precharge signal .o slashed. and the control signal CS. A selection circuit S26 calculates a logical sum of a logical product of a data signal DS on the data line D4 and the inverted control signal BCS and another logical product of the data signal DI and the control signal CS to produce an output signal RO.
The operation will be described with reference to FIG. 1. At first, when the control signal CS has the H level, the transistors P21 and P22 are put in an off state and the OR circuit O27 produces an output of the H level. Therefore, each of the AND circuits A29 and A30 outputs information on each of the address lines Al and A2 as it is and the transistor P28 is put in an off state. On the other hand, the selection circuit S26 is responsive to the control signal CS of the H level and selectively outputs an output of the inverter Ill, i.e., an output of the amplifier 101.
Next, when the control signal CS has the L level, the inverted control signal BCS has the H level. Therefore, the NOR circuits O23 and O24 produce outputs of the L level and the transistors N12 and N16 are turned into an off state to interrupt the continuous current path passing through the transistors N12 and N13 and the transistor P17. On the other hand, the transistors P21 and P22 are turned into an on state so that the H level is supplied to gates of the transistors P8 and P14 so that the transistors P8 and P14 are turned off. As a result, the continuous current passing through the transistors P14 and N13 and the transistors P8 and N9 is interrupted also. On the other hand, the selection circuit S26 is responsive to the control signal CS of the L level and selectively outputs the data DS as an output of a dynamic readout circuit 102. If the precharge signal .o slashed. has the L level, each of the AND circuits A29 and A30 produces an output of the L level. Therefore, the ROM cells M3 and M5 are put in an off state. In this period, the selection circuit S26 outputs the data on the data line D4 precharged, i.e., the H level. Subsequently, if the precharge signal .o slashed. is turned into the H level, the transistor P28 is turned off. If the address line A1 has the H level, the AND circuit A29 produces an output of the H level. However, since the drain of the ROM cell M3 is not connected to the data line D4, the data line D4 holds the precharged H level as memorized data and outputs the memorized data.
As described above, in the memory unit included in the conventional microcomputer, the control signal CS is set at the H level when the high-speed operation such as the operation at 20 MHz is required. Thus, a high-speed readout circuit using the current-sensing amplifier 101 is operated as a memory readout circuit to read from the memory at a high speed a program to be executed.
If a low-power-consumption operation is required in a low-speed operation such as on the order of 32 KHz, the control signal CS is set at the L level to switch the readout circuit into the dynamic readout circuit 102 which reads from the memory the program to be executed. The dynamic readout circuit 102 is substantially equivalent to a part which is formed by removing the current-sensing amplifier 101 from the memory circuit illustrated in FIG. 1. Considering the power consumption of the memory, power supply to the amplifier 101 consuming large electric power is stopped in response to the control signal CS. Accordingly, the dynamic readout circuit 102 requires current consumption corresponding to charge/discharge current of the bit lines alone. Thus, a low-power-consumption operation can be realized in the low-speed operation.
With the improvement in function of the microcomputer following the recent improvement in function of the mobile apparatus, the operation frequency is presently increased to the order of 10 times that of the prior art. If the high-speed operation is continuously carried out, the life of the battery is shortened due to large power consumption. This brings about the decrease in commercial value of the mobile apparatus. Taking the above into account, the low-speed operation mode on the order of 32 KHz is introduced as described in the foregoing in order to reduce the power consumption. Thus, the power consumption is reduced during the stand-by period.
In addition, development of programs in the C language as a high-grade language and increase in function of the mobile apparatus lead to the recent increase in program size. In order to cope with this, the memory (ROM) contained in the microcomputer is increased in size to the order of 10 times that of the prior art. Under the circumstances, even if the readout circuit for the program storage memory is implemented by the current-sensing amplifier and the dynamic readout circuit used in the high-speed operation and the low-speed operation, respectively, the power consumption during the low-speed operation is greater than that of the prior art because of the large memory size.
The reason why the power consumption is increased even in the low-speed operation will be described in the following.
Taking the charge and the discharge into consideration, the current consumption IB per bit line is given by: EQU IB=f(operation frequency KHz).multidot.C (load capacity PF).multidot.V.times.2
In case of an actual high-end microcomputer, an instruction code is read by every 32 bits (4 bytes) equal to a word length. It is therefore presumed that the number of data lines to be charged and discharged is equal to 16 on average.
In case of an ROM having a small memory size of several tens Kbytes, the load capacity per data line is about 5 pF. Assuming that the operation frequency during the low-power-consumption operation is equal to 32 KHz and that the operation voltage is equal to 3 V, the current consumption IBS is given by: EQU IBS=32.times.5.times.3.times.16(number of data lines).times.2=about 15 .mu. A
However, the size of the ROM is increased in recent years as described above. For example, in case of a typical latest ROM having a size of several hundreds Kbytes, a load capacity per data line is about 20 pF. In this event, the current consumption IBL is given by: EQU IBL=32.times.20.times.3.times.16.times.2=about 61 .mu.A
Even if the reading means similar to the memory of the conventional microcomputer is adopted, the current consumption is at least equal to about 61 .mu.A which corresponds to the power consumption of four times that of the prior art.
The conventional microcomputer described above has a structure such that an entire area of the program storage memory can be accessed even during the low-speed operation corresponding to the low power consumption. Therefore, with the increase in capacity of the program storage memory as a result of the increase in function, the current consumption corresponding to the charge/discharge current in memory access is increased to become unignorable.